1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to a memory device compatible with a synchronous static random access memory (SRAM) and a method of driving the same, in which the synchronous SRAM-compatible memory has dynamic random access memory cells and synchronizes with an external clock signal.
2. Description of the Related Art
As well known to those skilled in the art, a Random Access Memory (RAM), a type of semiconductor memory device, is generally classified into two types of memories, Static RAM (SRAM) and Dynamic RAM (DRAM). A general RAM includes a memory array composed of a plurality of unit memory cells arranged in a matrix form defined by rows and columns, and peripheral circuits adapted to control the input/output of data to/from the unit memory cells. Each of the unit memory cells in an SRAM stores one bit of data and has four transistors that form a latch structure and two transistors that serve as transmission gates. Since a general SRAM stores data in unit memory cells having latch structures, a refresh operation is not required to maintain the stored data. Further, the SRAM has the advantages of a fast operating speed and low power consumption compared to a DRAM.
However, since each unit memory cell of the SRAM is composed of six transistors, the SRAM disadvantageously requires a large wafer area compared to a DRAM in which each unit memory cell is implemented using a transistor and a capacitor. In more detail, in order to manufacture a semiconductor memory device of the same capacity, an SRAM requires a wafer area about six to ten times that of a DRAM. Such a large wafer area increases the unit cost of an SRAM. When a general DRAM instead of an SRAM is used to reduce the cost, a DRAM controller is additionally required to perform a periodic refresh operation. Further, the entire performance of a system is deteriorated due to the time required to perform the refresh operation and a slow operation speed.
In order to overcome the disadvantages of the DRAM and SRAM devices, attempts have been made to implement a SRAM to which DRAM memory cells are applied. One of these attempts is the technology of hiding a refresh operation by constructing a memory with a plurality of DRAM banks and a plurality of SRAM caches, thus making the memory compatible with an SRAM.
However, in the conventional technology, since a column address is continuously changed even though a column address is not received from the outside in the state where a word line for selecting a row of a memory array is kept activated, the burst access operation of inputting/outputting data to/from a specified memory cell cannot be implemented.